{"id":12463,"date":"2026-09-04T18:59:25","date_gmt":"2026-09-04T10:59:25","guid":{"rendered":"https:\/\/www.54iter.cn\/?vuln=cve-2026-53354"},"modified":"2026-09-04T18:59:25","modified_gmt":"2026-09-04T10:59:25","slug":"cve-2026-53354","status":"publish","type":"vuln","link":"https:\/\/www.54iter.cn\/?vuln=cve-2026-53354","title":{"rendered":"CVE-2026-53354 [HIGH] &#8211; In the Linux kernel, the following vulnerability has been resolved:\n\narm64: errata: Mitiga"},"content":{"rendered":"<p>In the Linux kernel, the following vulnerability has been resolved:<\/p>\n<p>arm64: errata: Mitigate TLBI errata on various Arm CPUs<\/p>\n<p>A number of CPUs developed by Arm suffer from errata whereby a broadcast<br \/>\nTLBI;DSB sequence may complete before the global observation of writes<br \/>\nwhich are translated by an affected TLB entry.<\/p>\n<p>These errata ONLY affect the completion of memory accesses which have<br \/>\nbeen translated by an invalidated TLB entry, and these errata DO NOT<br \/>\naffect the actual invalidation of TLB entries. TLB entries are removed<br \/>\ncorrectly.<\/p>\n<p>This issue has been assigned CVE ID CVE-2025-10263.<\/p>\n<p>To mitigate this issue, Arm recommends that software follows any<br \/>\naffected TLBI;DSB sequence with an additional TLBI;DSB, which will<br \/>\nensure that all memory write effects affected by the first TLBI have<br \/>\nbeen globally observed. The additional TLBI can use any operation that<br \/>\nis broadcast to affected CPUs, and the additional DSB can use any option<br \/>\nthat is sufficient to complete the additional TLBI.<\/p>\n<p>The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate<br \/>\nthe issue. Enable this workaround for affected CPUs, and update the<br \/>\nsilicon errata documentation accordingly.<\/p>\n<p>Note that due to the manner in which Arm develops IP and tracks errata,<br \/>\nsome CPUs share a common erratum number.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>In the Linux kernel, the following vulnerability has been resolved:<\/p>\n<p>arm64: errata: Mitigate TLBI errata on various Arm CPUs<\/p>\n<p>A number of CPUs developed by Arm suffer from errata whereby a broadcast<br \/>\nT<\/p>\n","protected":false},"template":"","meta":[],"categories":[],"tags":[],"class_list":["post-12463","vuln","type-vuln","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=\/wp\/v2\/vuln\/12463","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=\/wp\/v2\/vuln"}],"about":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=\/wp\/v2\/types\/vuln"}],"wp:attachment":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=12463"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.54iter.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=12463"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.54iter.cn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=12463"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}