In the Linux kernel, the following vulnerability has been resolved:<\/p>\n
mm: fix incorrect flush address in direct page table reclaim<\/p>\n
When zap_pte_range reclaims a page table, it does:<\/p>\n
pte_free_tlb(tlb, pmd_pgtable(pmdval), addr);<\/p>\n
and this is unconditionally wrong: if this code executes, addr *always*
\npoints one past the end of the range covered by the table. The addr
\nparameter is used to flush the TLB (really the paging-structure-cache)
\nto drop references to the to-be-freed table, and any architecture that
\ncares about the parameter will flush the wrong address. (But they’ll
\nstill free the correct page).<\/p>\n
I think it’s worth contemplating why the kernel works at all.<\/p>\n
If we hit the offending line of code, we will first clear the PMD entry
\n(line 1954, zap_empty_pte_table), then we will issue pending flushes if
\nforce_flush is set (tlb_flush_mmu_tlbonly(tlb)), then we will skip the
\nretry on line 1979 (phew!), and then we will do the offending
\npte_free_tlb call. *Or* we will clear the PMD entry immediately before
\npte_free_tlb (line 1983, zap_pte_table_if_empty).<\/p>\n
If we have any pending flushes (i.e. we actually zapped any last-level
\nentries) at the time we clear the PMD entry, then the flush really ought
\nto flush all references to the table (Linus certainly seems to think it
\nwill on all architectures [0]).<\/p>\n
The condition under which we have no accumulated flushes at the time of
\nthe clear is very complex (the whole zap_pte_range function has absurdly
\ncomplex control flow). If we do hit the bad case, then we will end up
\nclearing the PMD entry after the last time the range is flushed, and any
\nCPU is free to cache a reference to the (empty) page table. If this
\nhappens due to an ordinary read or write, it would segfault, so it would
\nbe rare. But the cache could be speculatively filled as well. Then
\nwe’ll flush the wrong address and then free and possibly reuse the
\ntable.<\/p>\n
On x86, even flushing the wrong address works on non-KPTI Intel systems
\nbecause INVLPG flushes *all* paging-structure-caches, not just the ones
\nfor the target address. But INVPCID does not, and flush_tlb_one_user
\nwill use INVPCID if it’s available. And then we’re toast. AMD systems
\nare more susceptible: we set the EFER.TCE bit, which makes even INVLPG
\nonly flush the target address.<\/p>\n
I think this might fix an issue in ripgrep reported here:
\nhttps:\/\/github.com\/BurntSushi\/ripgrep\/issues\/3494<\/p>\n
[0] https:\/\/lore.kernel.org\/all\/CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com\/T\/#u<\/p>\n","protected":false},"excerpt":{"rendered":"
In the Linux kernel, the following vulnerability has been resolved:<\/p>\n
mm: fix incorrect flush address in direct page table reclaim<\/p>\n
When zap_pte_range reclaims a page table, it does:<\/p>\n
pte_free_tlb(<\/p>\n","protected":false},"template":"","meta":[],"categories":[],"tags":[],"class_list":["post-11257","vuln","type-vuln","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=\/wp\/v2\/vuln\/11257","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=\/wp\/v2\/vuln"}],"about":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=\/wp\/v2\/types\/vuln"}],"wp:attachment":[{"href":"https:\/\/www.54iter.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=11257"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.54iter.cn\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=11257"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.54iter.cn\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=11257"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}